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1 features ? am/fm tuner front end with integrated pll am up-conversion system (am-if: 10.7 mhz) fm down-conversion system (fm-if: 10.7 mhz) if frequencies up to 25 mhz fine-tuning steps: am = 1 khz and fm = 50 khz/25 khz/12.5 khz fast fractional pll (lock time < 1 ms) inclusive spurious compensation fast rf-agc, programmable in 1-db steps fast if-agc, programmable in 2-db steps fast frequency change by 2 programmable n-divider two dacs for automatic tuner alignment high s/n ratio 3-wire bus (enable, clock and data; 3 v and 5 v microcontrollers-compatible) electrostatic sensitive device. observe precautions for handling. description the t4260 is an advanced am/fm receiver with integrated fast pll as a single-chip solution based on atmel?s high-performance bicmos ii technology. the low-imped- ance driver at the if output is designed for the a/d of a digital if. the fast tuning concept realized in this part is based on patents held by atmel and allows lock times less than 1 ms for a jump over the fm band with a step width of 12.5 khz. the am up- conversion and the fm down-conversion allows an economic filter concept. an auto- matic tuner alignment is provided by built-in dacs for gain and offset compensation. the frequency range of the ic covers the fm broadcasting band as well as the am band. the low current consumption helps the designers to achieve economic power consumption concepts and helps to keep the power dissipation in the tuner low. pin description figure 1. pinning sso44 d a c 1 d a c 2 f m a g c o m x f m i a m x f m i b g n d r f m x a m i b m x a m i a a m a g c o i f a g c a 2 s w 2 / a g c r f a g c a 2 s w 1 v r v c o v s p l l f m l f a m l f v t u n e o s c g n d o s c e o s c b o s c b u f e n c l k d a t a v r p l l r e f f r e q g n d p l l i f o u t b i f o u t a i f a g c f m i f a g c a 1 r f a g c f m i f r e f i f i n a m i f i n f m v r t g n d t m x a m o b m x a m o a v s t r f a g c a 1 m x f m o a m x f m o b 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 4 4 4 3 4 2 4 1 4 0 3 9 3 8 3 7 3 6 3 5 3 4 3 3 3 2 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 am/fm front end ic t4260 preliminary rev. 4528b ? audr ? 04/02
2 t4260 4528b ? audr ? 04/02 pin description pin symbol function 1 dac1 dac1 output 2 dac2 dac2 output 3 fmagco fm agc current 4 mxfmia fm mixer input a 5 mxfmib fm mixer input b 6 gndrf rf ground 7 mxamib am mixer input b 8 mxamia am mixer input a 9 amagco am agc current 10 ifagca2 am if-agc filter 2 11 sw2/agc switch 2 / am agc voltage 12 rfagca2 rf am-agc filter 2 13 sw1 switching output 1 14 vrvco vco reference voltage 15 vspll pll supply voltage 16 fmlf fm loop filter 17 amlf am loop filter 18 vtune tuning voltage 19 oscgnd oscillator ground 20 osce oscillator emitter 21 oscb oscillator base 22 oscbuf oscillator buffer output / input 23 en 3-wire bus enable 24 clk 3-wire bus clock 25 data 3-wire bus data 26 vrpll pll reference voltage 27 reffreq pll reference frequency 28 gndpll pll ground 29 ifoutb if output b 30 ifouta if output a 31 ifagcfm fm if-agc filter 32 ifagca1 am if-agc filter 1 33 rfagcfm rf fm-agc filter 34 ifref if amplifier reference input 35 ifinam if amplifier am input 36 ifinfm if amplifier fm input 37 vrt tuner reference voltage 38 gndt tuner ground 39 mxamob am mixer output b 40 mxamoa am mixer output a 41 vst tuner supply voltage 42 rfagca1 rf am-agc filter 1 43 mxfmoa fm mixer output a 44 mxfmob fm mixer output b
3 t4260 4528b ? audr ? 04/02 figure 2. block diagram functional description the t4260 implements an am up-conversion reception path from the rf input signal to the if output signal. a vco and an lo prescaler for am are integrated to generate the lo frequency to the am mixer. the fm reception path generates the same lo fre- quency from the rf input signal by a down-conversion to the if output. the if a/d output is designed for digital signal processing. the if can be chosen in the range of 10 mhz to 25 mhz. automatic gain control (agc) circuits are implemented to control the preamplifier stages in the am and fm reception paths. for improved performance, the pll has an integrated special 2-bit shift fractional logic with spurious suppression that enables fast frequency changes in am and fm mode by a low step frequency (f pdf ). in addition, two programmable dacs (digital-to-analog converter) support the alignment via a microcontroller. for a double-tuner concept, external voltage can be applied at the input of the dacs, the internal pll can switched off and the osc buffer (output) can also be used as input. several register bits (bit 0 to bit 145) are used to control the circuit ? s operation and to adapt certain circuit parameters to the specific application. the control bits are orga- nized in four 8-bit, four 16-bit and three 24-bit registers that can be programmed by the 3-wire bus protocol. the bus protocol and the bit-to-register mapping is described in the section ? 3-wire bus description ? . the meaning of the control bits is mentioned in the following sections. agc pll supply agc div n div r div pd rf/if supply bus vco fmagco gndrf mxamib mxamia mxfmib mxfmia amagco am fm 43 mxfmob mxamob mxamoa ifref ifinam ininfm ifoutb ifouta ifagcfm ifagca1 vst vrt gndt vspll vrpll gndpll en clk data sw1 sw2/agc vtune amlf fmlf reffreq oscgnd osce oscb oscbuf rfagca2 rfagcfm rfagca1 vrvco dac1 dac2 ifagca2 sw-amlf mxfmoa 44 39 40 34 35 36 29 30 31 10 32 41 37 38 14 15 26 28 23 24 25 11 13 2 1 16 17 18 22 21 20 19 27 4 5 6 7 8 42 33 12 9 3
4 t4260 4528b ? audr ? 04/02 absolute maximum ratings all voltages are referred to gnd parameters symbol value unit analog supply voltage pins 15 and 41 v st , v spll 10 v maximum power consumption p tot 1.0 w ambient temperature range t amb -40 to +85 c storage temperature range t stg -40 to +150 c junction temperature t j 150 c thermal resistance parameters symbol value unit junction ambient, soldered to pcb r thja 52 k/w operating range parameters symbol min. typ. max. unit supply voltage range pins 15 and 41 v st , v spll 88.510v supply current pins 15 and 41 i s 70 100 ma ambient temperature t amb -40 85 c oscillator frequency pin 21 r fi 60 175 mhz electrical characteristics test conditions (unless otherwise specified): v st /v spll = +8.5 v, t amb = +25 c no. parameters test conditions pin symbol min. typ. max. unit type* 1 pll divider 1.1 programmable r-divider 14-bit register 316,383a 1.2 programmable (vco) n-divider (1 khz step frequency) 2- 18-bit register switchable via bit 5 3 262,143 a 1.3 reference oscillator input voltage f = 0.1 mhz to 3 mhz 27 100 mv rms b 1.4 reference frequency fm am 120 120 10,000 10,000 khz khz c 1.5 settling time in fm mode (switching from 87.5 mhz to 108 mhz or vice versa) f pd = 50 khz i pd = 2 ma 1msb *) type means: a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter
5 t4260 4528b ? audr ? 04/02 2 amlf/fmlf 2.1 output current 1 fmlf, amlf = 1.8 v 16, 17 40 50 60 a a 2.2 output current 2 fmlf, amlf = 1.8 v 16, 17 80 100 120 a a 2.3 output current 3 fmlf, amlf = 1.8 v 16, 17 850 500 1250 a a 2.4 output current 4 fmlf, amlf = 1.8 v 16, 17 1650 2000 2450 a a 2.5 leakage current fmlf, amlf = 1.8 v 16, 17 10 na a 3 vtune 3.1 saturation voltage low v sath = (v a -v pdofm ) 18 v satl 100 200 400 mv c 3.2 saturation voltage high v sath = (v a -v pdofm ) 18 v sath 500 mv c 4 dac1, dac2 4.1 output current 1, 2 i dac1,2 1mad 4.2 output voltage 1, 2 v dac1,2 0.3 v s -0.5 v c 4.3 maximum offset range offset = 0, gain = 58 1, 2 0.9 0.98 1.1 v a 4.4 minimum offset range offset = 127, gain = 58 1, 2 0.9 -0.98 -1.1 v a 4.5 maximum gain range gain = 255, offset = 64 1, 2 2.06 2.09 2.13 a 4.6 minimum gain range gain = 0, offset = 64 1, 2 0.63 0.67 0.73 a 5 oscillator 5.1 frequency range 21 60 170 mhz b 5.1 buffer output 22 150 mv rms c 6 oscillator input 6.1 input voltage 21 v osc 150 mv rms a 7 fm mixer 7.1 frequency range 75 163 mhz b 7.2 input ip3 133 dbv c 7.3 input impedance 3.5 k ? d 7.4 input capacitance 4pfd 7.5 noise figure f 10 db c 7.6 conversion transconductance 2.6 3.1 3.6 ms d 8 am mixer (symmetrical input) 8.1 frequency range 0.075 26 mhz b 8.2 input ip3 133 dbv c 8.3 input impedance 2.5 k ? d 8.4 noise figure f 10 db c electrical characteristics (continued) test conditions (unless otherwise specified): v st /v spll = +8.5 v, t amb = +25 c no. parameters test conditions pin symbol min. typ. max. unit type* *) type means: a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter
6 t4260 4528b ? audr ? 04/02 8.5 conversion transconductance 2.6 3.1 3.6 ms d 9isolation 9.1 isolation am-fm 40 db c 9.2 if suppression 40 db c 10 rf-agc 10.1 frequency range fm am 75 0.075 163 26 mhz mhz a 10.2 output current fm am 5 5 ma ma b 10.3 output current time constant fm rising fm falling am symmetrical 2 50 40 ms ms ms c 10.4 rf-agc am threshold (programmable with bit 12 - bit 15) 88 dbv 42 87 88 90 dbv a 89 dbv 42 88 89 91 dbv a 90 dbv 42 89 90 92 dbv a 91 dbv 42 90 91 93 dbv a 92 dbv 42 91 92 94 dbv a 93 dbv 42 92 93 95 dbv a 94 dbv 42 93 94 96 dbv a 95 dbv 42 94 95 97 dbv a 96 dbv 42 95 96 98 dbv a 97 dbv 42 96 97 99 dbv a 98 dbv 42 97 98 100 dbv a 99 dbv 42 98 99 101 dbv a 100 dbv 42 99 100 102 dbv a 101 dbv 42 100 101 103 dbv a 102 dbv 42 101 102 104 dbv a 103 dbv 42 102 103 107 dbv a electrical characteristics (continued) test conditions (unless otherwise specified): v st /v spll = +8.5 v, t amb = +25 c no. parameters test conditions pin symbol min. typ. max. unit type* *) type means: a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter
7 t4260 4528b ? audr ? 04/02 10.5 rf-agc fm threshold (programmable with bit 12 - bit 15) 91 dbv 33 90 91 93 dbv a 92 dbv 33 91 92 95 dbv a 93 dbv 33 92 93 96 dbv a 94 dbv 33 93 94 96 dbv a 95 dbv 33 94 95 98 dbv a 96 dbv 33 95 96 99 dbv a 97 dbv 33 96 97 102 dbv a 98 dbv 33 97 98 101 dbv a 99 dbv 33 98 99 102 dbv a 100 dbv 33 99 100 104 dbv a 101 dbv 33 100 101 104 dbv a 102 dbv 33 101 102 105 dbv a 103 dbv 33 102 103 106 dbv a 104 dbv 33 103 104 107 dbv a 105 dbv 33 104 105 108 dbv a 106 dbv 33 105 106 109 dbv a 11 if amplifier 11.1 frequency range 10 25 mhz a 11.2 output voltage 117 dbv b 11.3 distortion (2-tone im3) f1 = 10.7 mhz f2 = 10.75 mhz rl = 2 300 ? 55 db a 11.4 gain (programmable in 2-db steps) minimum gain maximum gain 12 42 db db a 11.5 input impedance fm am 36, 35 330 2500 ? ? d 11.6 output impedance 600 ? between pin 29 and pin 30 29, 30 13 ? c 12 if-agc 12.1 if-agc am/fm threshold (programmable with bit 0 - bit 2) 109 dbv 29/30 108 109 112 dbv a 111 dbv 29/30 110 111 114 dbv a 113 dbv 29/30 111 113 115 dbv a 115 dbv 29/30 113 115 117 dbv a 117 dbv 29/30 116 117 121 dbv a 118 dbv 29/30 117 118 122 dbv a 119 dbv 29/30 118 119 123 dbv a 121 dbv 29/30 120 121 126 dbv a 12.2 agc dynamic range tbd db b 12.3 agc time constant (external capacity 100 nf) fm rising fm falling am symmetrical 16 4 200 s ms ms d electrical characteristics (continued) test conditions (unless otherwise specified): v st /v spll = +8.5 v, t amb = +25 c no. parameters test conditions pin symbol min. typ. max. unit type* *) type means: a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter
8 t4260 4528b ? audr ? 04/02 13 if gain 13.1 if gain (programmable with bit 6 - bit 9) 12 db 9 12 14 db a 14 db 12 14 16 db a 16 db 14 16 18 db a 18 db 17 18 20 db c 20 db 17 20 22 db a 22 db 19 22 24 db c 24 db 21 24 26 db c 26 db 23 26 28 db c 28 db 25 28 30 db a 30 db 27 30 32 db c 32 db 29 32 34 db c 34 db 31 34 36 db c 36 db 33 36 38 db c 38 db 35 38 40 db c 40 db 37 40 42 db c 42 db 39 42 44 db a 14 swo1 (open drain) 14.1 output voltagelow i = 1 ma, v swo1 = 8.5 v 13 v swol 100 160 200 mv a 14.2 output leakage current high 13 i ohl 10 a a 14.3 maximum output voltage 13 8.5 v c 15 sw2/agc (open drain in switch mode) 15.1 output voltage low i = 1 ma, v11 = 6 v 11 v swol 100 160 200 mv a 15.2 output leakage current high 11 i ohl 10 a a 15.3 maximum output voltage 11 6 v c 16 3-wire bus, enable, data, clock 16.1 input voltage high low 23-25 v bus v bus 2.7 -0.3 5.3 0.8 v v a a 16.2 clock frequency 24 1.0 mhz b 16.3 period of clk 24 t h t l 250 250 ns ns c c 16.4 rise time en, da, clk 23-25 t r 400 ns c 16.5 fall time en, da, clk 23-25 t f 100 ns c 16.6 set-up time 23-25 t s 100 ns c 16.7 hold time en 23 t hen 250 ns c 16.8 hold time da 25 t hda 0 ns c electrical characteristics (continued) test conditions (unless otherwise specified): v st /v spll = +8.5 v, t amb = +25 c no. parameters test conditions pin symbol min. typ. max. unit type* *) type means: a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter
9 t4260 4528b ? audr ? 04/02 3-wire bus description the register settings of the t4260 are programmed by a 3-wire bus protocol. the bus protocol consists of separate commands. a defined number of bits is transmitted sequentially during each command. one command is used to program all bits of one register. the different registers avail- able (see chapter ? 3-wire bus data transfer ? ) are addressed by the length of the command (number of transmitted bits) and by two address bits that are unique to each register of a given length. 8-bit registers are programmed by 8-bit commands, 16-bit reg- isters are programmed by 16-bit commands and 24-bit registers are programmed by 24- bit commands. each bus command starts with a falling edge on the enable line (en) and ends with a rising edge on en. en has to be kept low during the bus command. the sequence of transmitted bits during one command starts with the msb of the first byte and ends with the lsb of the last byte of the register addressed. to transmit one bit (0/1), data has to be set to the appropriate value (low/high) and a high-to-low transition has to be performed on the clock line (clk) while data is valid. the data is evaluated at the falling edges of clk. the number of high-to-low transitions on clk during the low period of en is used to determine the length of the command. figure 3. 3-wire pulse diagram 11 8-bit command en clk data msb lsb byte 1 24-bit command 16-bit command data clk msb msb lsb lsb byte 1 byte 2 en en clk data msb msb lsb lsb byte 3 byte 2 lsb msb byte 1 en e.g. r-divider 2 2 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 x x 2 13 2 12 2 2 10 r-divider addr. vco-divider 2 9 2 8 0 1 fract. pdam 2 2 pdfm 3 2 1 0
10 t4260 4528b ? audr ? 04/02 figure 4. 3-wire bus timing diagram t f t r t r t s t hen t hda t f t h t l enable data clock v high t s t r t f v low v high v low v high v low
11 t4260 4528b ? audr ? 04/02 3-wire bus data transfer table 1. control registers a24_10 msb byte 1 lsb msb byte 2 lsb msb byte 3 ls b r-divider r-divider addr. pdam/ pdfm frac- tional divider vco 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 xx2 13 2 12 2 11 2 10 2 9 2 8 10 1/0 0/1 2 3 2 2 2 1 2 0 131 130 129 128 127 126 125 124 139 138 137 136 135 134 133 132 x x 145 144 143 142 141 140 a24_01 msb byte 1 lsb msb byte 2 lsb msb byte 3 lsb n2-divider n2-divider addr. x x x x n2-divider 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 2 15 2 14 2 13 2 12 2 11 2 10 2 9 2 8 01 0 0 0 0 2 17 2 16 109 108 107 106 105 104 103 102 117 116 115 114 113 112 111 110 x x 123 122 12 1 12 0 11 9 118 a24_00 msb byte 1 lsb msb byte 2 lsb msb byte 3 lsb n1-divider n1-divider addr. x x x x n1-divider 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 2 15 2 14 2 13 2 12 2 11 2 10 2 9 2 8 00 0 0 0 0 2 17 2 16 87 86 85 84 83 82 81 80 95 94 93 92 91 90 89 88 x x 101 100 99 98 97 96 a16_11 msb byte 1 lsb msb byte 2 lsb dac2-gain addr. 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 11x x xxxx 73 72 71 70 69 68 67 66 x x 79 78 77 76 75 74 a16_10 msb byte 1 lsb msb byte 2 lsb dac2-offset addr. sw- amlf osc.- buffe r lo w c. cp hi gh c. cp sw- impul se sw- wire x2 6 2 5 2 4 2 3 2 2 2 1 2 0 10 1 = stand ard on/ off hi/ lo hi/ lo on/ off on/o ff 59 58 57 56 55 54 53 52 x x 65 64 63 62 61 60 a16_01 msb byte 1 lsb msb byte 2 lsb dac1-gain addr. 1=s w2 0=a gc sw2 1=lo w sw1 1=lo w 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 0 1 x x x 1/0 1/0 1/0 45 44 43 42 41 40 39 38 x x 51 50 49 48 47 46
12 t4260 4528b ? audr ? 04/02 a16_00 msb byte 1 lsb msb byte 2 lsb dac1-offset addr. x x x x x sh_ direct x2 6 2 5 2 4 2 3 2 2 2 1 2 0 00 0 0 0 0 1/0 1/0 31 30 29 28 27 26 25 24 x x 37 36 35 34 33 32 a8_11 msb byte 1 lsb addr. delay time high cur. cp2 delay time high cur. cp1 x hcd el/ _dire ct 11 on/ off hi/l o on/ off hi/ lo 01/0 x x 23 22 21 20 19 18 a8_10 msb byte 1 lsb addr. am/f m if- agc rf-agc 10 1/0 1/0 2 3 2 2 2 1 2 0 x x 17 16 15 14 13 12 a8_01 msb byte 1 lsb addr. if-in vco if-gain 01 am/f m hi/l o 2 3 2 2 2 1 2 0 xx 11 10 9 8 7 6 a8_00 msb byte 1 lsb addr. n2/n 1 pll on/ off pd te/ pd if-agc 0 0 1/0 1/0 1/0 2 2 2 1 2 0 xx 5 4 3 2 1 0
13 t4260 4528b ? audr ? 04/02 bus control if-agc the if-agc controls the level of the if signal that is passed to the external ceramic filter and the if input (am pin 35 or fm pin 36 and pin 34). in am mode the time constant can be selected by the external capacitors at pin 32 (ifagca1) and pin 10 (ifagca2) and in fm mode by an external capacitor at pin 31 (ifagcfm). in am mode, the double pole (by the capacitors at pin 32 and pin 10) allows a better harmonic distortion by a lower time constant. the if-agc gain can be controlled by setting bits 0 to 2 as given in table 2. table 2. if-agc gain the if-agc on/off can be controlled by bit 16 as given in table 3. table 3. if-agc pd test only in fm mode, the locked and unlocked condition of the pll can be signaled at the amlf-pin (pin 17) by activation of pd test (bit 3 = 1). the locked pll (in fm mode) is signaled by a high level (5 v) and the unlocked pll by a low level (0 v) at pin 17. for the use of pd test, it is necessary to interrupt the external am loop filter to vtune (pin 18) and to fmlf (pin 16). moreover, the loop filter operating mode has to be set to pdfm active (bit 145 = 0). table 4. pd-test mode n1/n2 the n2/n1 bit controls the active n-divider. only one of the two n-divider can be active. the n1-divider is activated by setting bit 5 = 0, the n2-divider by setting bit 5 = 1. table 5. n-divider if-agc b2 b1 b0 109 dbv 0 0 0 111 dbv 0 0 1 113 dbv 0 1 0 115 dbv 0 1 1 117 dbv 1 0 0 118 dbv 1 0 1 119 dbv 1 1 0 121 dbv 1 1 1 if-agc on/off b16 if-agc on 1 if-agc off 0 pd te/pd b3 pin 17 = amlf output (standard) 0 pin 17 = lock detect output 1 n2/n1 b5 n1-divider active 0 n2-divider active 1
14 t4260 4528b ? audr ? 04/02 if amplifier the if gain amplifier can be used in am and fm mode to compensate the loss of the external ceramic bandfilters. the if gain can be controlled in 2-db steps by setting bit 6 to bit 9 as given in table 6. table 6. if gain the selection of the if amplifier input can be controlled by bit 11 as given in table 7. table 7. if-in operating mode remark: the am input (pin 35) has an input impedance of 2.5 k ? for matching with a crystal filter. the fm input (pin 36) has an input impedance of 330 ? for matching with a ceramic filter. vco the vco hi/lo function is controlled by means of bit 10. table 8. vco operating mode rf-agc the am and fm rf-agc controls the current into the am and fm pin diodes (fm pin 3 and am pin 9) to limit the level at the am or fm mixer input. if the level at the am or fm mixer input exceeds the selected threshold, then the current into the am or fm pin diodes increases. if this step is not sufficient in am mode, the source drain voltage of the mosfet (pin 11) can be decreased. in am mode, the time constants can be selected by the external capacitors at pin 42 (rfagca1) and at pin 12 (rfagcam2) and in fm mode by an external capacitor at pin 33 (rfagcfm). in am mode, the dou- ble pole (by the capacitors at pin 42 and pin 12) allows a better harmonic distortion by a lower time constant. the rf-agc can be controlled in 1-db steps by setting the bits 12 to 15. the values for fm and am are controlled by bit 17. if gain b9 b8 b7 b6 12 db 0 0 0 0 14 db 0 0 0 1 16 db 0 0 1 0 18 db 0 0 1 1 20 db 0 1 0 0 ... ... ... ... ... 40 db 1 1 1 0 42 db 1 1 1 1 if-in am/fm b11 if-in fm 0 if-in am 1 vco hi/lo b10 vco high current 0 vco low current 1
15 t4260 4528b ? audr ? 04/02 table 9. rf-agc reception mode there are two different operation modes, am and fm, which are selected by means of bit 17 and bit 145 according to table 1 and table 2. in am mode (bit 17 = 1), the am mixer, the am rf-agc, the am divider (prescaler) and the if am amplifier (input at pin 35) are activated. in fm mode (bit 17 = 0), the fm mixer, the fm rf-agc and the if fm amplifier (input at pin 36) are activated. in am or fm reception mode, bit 145 has to be set to the corresponding mode. the buffer amplifier input can be connected to pin 16 (with the external fm loop filter) by bit 145 = 0 and to pin 17 (with the external am loopfilter) by bit 145 = 1. the am/fm function for the tuner part is controlled by bit 17 as given in table 10. table 10. tuner operating modes pll the pll can switch off by bit 4 = 0. in this case, the n-divider signal is internally connected to ground. table 11. pll mode there are two registers, hcdel 1 (bits 20 and 21) and hcdel 2 (bits 22 and 23), to control the delay time of the high-current charge pump and to deactivate them. bit 18 (hcdel_direct) determine whether register hcdel 1 or 2 is used. bit 18 is used to select between hcdel 1 and hcdel 2. table 12. high-current charge pump delay time register rf-agc am rf-agc fm b15 b14 b13 b12 88 db 91 db 0 0 0 0 89 db 92 db 0 0 0 1 90 db 93 db 0 0 1 0 91 db 94 db 0 0 1 1 92 db 95 db 0 1 0 0 ... ... ... ... ... ... 102 db 105 db 1 1 1 0 103 db 106 db 1 1 1 1 am/fm b17 fm 0 am 1 pll on/off b4 pll off 0 pll on 1 hcdel 1/2 select mode hcdel_ direct b18 direct hcdel 1 0 direct hcdel 2 1
16 t4260 4528b ? audr ? 04/02 if bits 20 and 21 (hcdel 1) or bits 22 and 23 (hdcel 2) are both set to 0, then the high-current charge pump is deactivated. otherwise, the delay time can be selected as described in table 13. table 13. delay time of hcdel register the shift-direct function can also be controlled by bit 32 and bit 33 as follows. if bit 32 = 0, the r/n-divider is shifted by two bits to the right. a divider 2-bit shift (bit 32 = 0) allows faster frequeny changes by using a four times higher step frequeny (e.g., f pdf = 50 khz instead of f pdf = 12.5 khz). if the pll is locked (after the frequency change), the normal step frequency (e.g., f pdf = 12.5 khz) will be active again. if no 2-bit shift is used bit 32 = 1), the frequeny changes will be done with the normal step frequency (12.5 khz). table 14. manual and lock detect shift mode sw1 the switching output sw1 (pin 13) is controlled by bit 46 as given in table 15. table 15. switching output remark: sw1 is an open-drain output. figure 5. internal components at sw1 high-current charge pump b21/b23 b20/b22 off 0 0 delay time 5 ns 0 1 delay time 10 ns 1 0 delay time 15 ns 1 1 sh_ld control sh_direct b32 dividers 2-bit shift 0 no shift 1 sw1 b46 high 0 low 1 sw1
17 t4260 4528b ? audr ? 04/02 sw2/agc the pin sw2/agc works as a switching output (open drain, pin 11) or as an am agc- control pin to control the cascade stage of an external am-preamplifier. the sw2/agc is controlled by bits 47 and 48 as given in table 16. table 16. switching output 2 / agc mode remark: in agc mode, the output voltage is 6 v down to 1 v. figure 6. internal components at sw2/agc test mode a special test mode is implemented for final production test only. this mode is activated by setting bit 123 = 1. this mode is not intended to be used by customer application. for normal operation bit 123 has to be set to 0. table 17. test mode am mixer the am mixer is used for up-conversion of the am reception frequency to the if frequency. therefore, an am prescaler is implemented to generate the necessary lo frequency from the vco frequency. the vco divider can be controlled by the bits 140 to 143 as given in table 18. (the vco divider is only active in am mode) table 18. divider factor of the am prescaler sw2/agc b48 b47 agc function 0 x high 1 0 low 1 1 swo/agc v s agc sw2 test mode b123 on 1 off 0 divider am prescaler b143 b142 b141 b140 divide by 2 0 0 0 0 divide by 3 0 0 0 1 divide by 4 0 0 1 0 divide by 5 0 0 1 1 divide by 6 0 1 0 0 divide by 7 0 1 0 1 divide by 8 0 1 1 0 divide by 9 0 1 1 1 divide by 10 1 x x x
18 t4260 4528b ? audr ? 04/02 fm mixer in the fm mixer stage, the fm reception frequency is down-converted to the if frequency. the vco frequency is used as lo frequency for the mixer. pll loop filter the pll loop filter selection for am and fm mode can be controlled by bit 145 as given in table 19. table 19. loop filter operating mode fractional mode the activated fractional mode (bit 144 = 0) in connection with the direct shift (bit 32 = 0) allows fast frequency changes (with the help of the 2-bit shift) with a four times higher step frequency. after the frequency change, the normal step frequency is active again. if the fractional mode is deactivated (bit 144 = 1) and direct shift mode is active, (bit 32 = 0) the vco frequency is set to the next lower frequency which is many times the amount frequency of 4 times step frequency. this means that the 2 shifted bits of the active n-divider are not used in this mode. the shift bits are interpreted as logic 0. the fractional mode with direct shift mode deactivated (bit 32 = 1) allows normal fre- quency changes with a step frequency of 12.5 khz. table 20. fractional mode spurious suppression in fractional and direct shift mode the spurious suppression is able by sw wire and sw impulse. table 21. spurious suppression by sw wire table 22. spurious suppression by correction current charge pump charge pump (amlf/fmlf) amlf/fmlf is the current charge pump output of the pll. the current can be con- trolled by setting the bits 62 and 63. the loop filter has to be designed correspondingly to the chosen pump current and the internal reference frequency. during the frequency change, the high-current charge pump (bit 62) is active to enable fast frequency changes. after the frequency change, the current will be reduced to guar- antee a high s/n ratio. the low-current charge pump (bit 63) is then active. the high current charge pump can also be switched off by setting the bits of the active hcdel register to 0 (bit 20 and bit 21 [hcdel 1] or bit 22 and bit 23 [hcdel 2]). the current of the high-current charge pump is controlled by bit 62 as given in table 23. pdam/pdfm b145 pdfm active 0 pdam active 1 fractional b144 on 0 off 1 sw wire b60 off 0 on 1 sw impulse b61 off 0 on 1
19 t4260 4528b ? audr ? 04/02 table 23. high-current charge pump the current of the low-current charge pump is controlled by bit 63 as given in table 24. table 24. low-current charge pump external voltage at amlf (oscillator) the oscillator (pin 22) can be switched on/off by bit 65. it is possible to use the oscillator buffer as an input or as an output. at the amlf (pin 17), an external tuning voltage can be applied (bit 65 = 0). if this is not done, the ic operates in standard mode (bit 65 = 1). the oscillator, oscillator buffer and the amlf are controlled by the bits 65 and 64 as given in table 25. table 25. oscillator operating modes dac1, 2 for automatic tuner alignment, the dac1 and dac2 of the ic can be controlled by set- ting gain and offset values. the principle of the operation is shown in figure 7. the gain is in the range of 0.67 v tune to 2.09 v tune . the offset range is +0.98 v to -0.98 v. for alignment, dac1 and dac2 are connected to the varicaps of the preselection filter and the if filter. for alignment, offset and gain are set for having the best tuner tracking. figure 7. block diagram of dac1, 2 high-current charge pump b62 1 ma 0 2 ma 1 low current charge pump b63 50 a 0 100 a 1 oscillator oscillator buffer amlf (pin 17) b65 b64 off input input f. dac ? s 0 x on off amlf (standard) 1 0 on output amlf (standard) 1 1 vtune offset gain dac1, 2 +/-
20 t4260 4528b ? audr ? 04/02 the gain of dac1 and dac2 has a range of approximately 0.67 v(vtune) to 2.09 v(tune). this range is divided into 255 steps. one step is approximately (2.09- 0.67)/255 = 0.00557 m v(tune). the gain of dac1 can be controlled by the bits 38 to 45 (2 0 to 2 7 ) and the gain of dac2 can be controlled by the bits 66 to bit 73 (2 0 to 2 7 ) as given in table 26. table 26. gain of dac1, 2 offset = 64 the offset of dac1 and dac2 has a range of approximately +0.98 v to -0.99 v. this range is divided into 127 steps. one step is approximately 1.97 v/127 = 15.52 mv. the offset of dac1 can be controlled by the bits 24 to bit 30 (2 0 to 2 6 ) and the offset gain of dac2 can be controlled by the bits 52 to bit 58 (2 0 to 2 6 ) as given in table 27. table 27. offset of dac1, 2 gain = 58 gain dac1 approximately b45 b44 b43 b42 b41 b40 b39 b38 decimal gain gain dac2 approximately b73 b72 b71 b70 b69 b68 b67 b66 decimal gain 0.6728 v(tune) 0 0 0 0 0 0 0 0 0 0.6783 v(tune) 0 0 0 0 0 0 0 1 1 0.6838 v(tune) 0 0 0 0 0 0 1 0 2 0.6894 v(tune) 0 0 0 0 0 0 1 1 3 ... ... ... ... ... ... ... ... ... ... 0.9959 v(tune) 0 0 1 1 1 0 1 0 58 ... ... ... ... ... ... ... ... ... ... 2.0821 v(tune) 1 1 1 1 1 1 0 1 253 2.0877 v(tune) 1 1 1 1 1 1 1 0 254 2.0932 v(tune) 1 1 1 1 1 1 1 1 255 offset dac1 approximately b30 b29 b28 b26 b26 b25 b24 decimal offset offset dac2 approximately b58 b57 b56 b55 b54 b53 b52 decimal offset 0.9815 v 0 0 0 0 0 0 0 0 0.9659 v 0 0 0 0 0 0 1 1 0.9512 v 0 0 0 0 0 1 0 2 0.9353 v 0 0 0 0 0 1 1 3 ... ... ... ... ... ... ... ... -0.0120 v 1 0 0 0 0 0 0 64 ... ... ... ... ... ... ... ... -0.9576 v 1 1 1 1 1 0 1 125 -0.9733 v 1 1 1 1 1 1 0 126 -0.9890 v 1 1 1 1 1 1 1 127
21 t4260 4528b ? audr ? 04/02 figure 8. internal components of dac1, 2 input/output interface circuits vtune, amlf and fmlf vtune is the loop amplifier output of the pll. the bipolar output stage is a rail-to-rail amplifier. figure 9. internal components at v tune , amlf and fmlf en, data, clk all functions can be controlled via a 3-wire bus consisting of enable, data and clock. the bus is designed for microcontrollers which can operate with 3-v supply voltage. details of the data transfer protocol can be found in the chapter ? 3-wire bus description ? . figure 10. internal components at enable, data and clock vs dac1, 2 amlf/fmlf v s vtune v5 v s v 5 en data clk
22 t4260 4528b ? audr ? 04/02 application information high-speed tuning the fractional mode (bit 144 = 0) in connection with the direct shift mode (bit 32 = 0) allows very fast frequency changes with four times the step frequency (50 khz = 4 f pdf ) at low frequency steps (e.g., f pdf = 12.5 khz). in direct shift mode, the r- and the n-divider are shifted by 2 bits to the right (this corresponds to a r- and n-divider division by 4 or a step frequency multiplication by 4). due to the 2-bit shift, a faster tuning response time of approximately 1 ms instead of 3- 4 ms for a tune over the whole fm band from 87.5 mhz to 108 mhz is possible with f pdf = 12.5 khz. if the fm receiving frequency is 103.2125 mhz (with e.g. f pdf = 12.5 khz and f if = 10.7 mhz), an n-divider of 9113 and an r-divider of 12 are necessary when using a reference-frequency (fref) of 150 khz. f vco = f if + f rec = 10.7 mhz + 103.2125 mhz = 113.9125 mhz f pdf = f vco / n = f ref / r = 113.9125 mhz / 9113 = 150 khz /12 = 12.5 khz an important condition for the use of the fractional mode is an r-divider with an integer value after the division by 4 (r-dividers have to be a multiple of 4). after a 2-bit shift (divider division by 4), the r-divider is now 3 (instead of 12) and the n-divider is 2278.25 (instead of 9113). the new n-divider of 2278.25 is also called ? fractional step because the modulo value of the n-divider is 0.25 = ? . in total, there are 4 different fractional 2-bit shift steps: full, ? , ? and ? step. if the fractional mode is switched off (bit 144 = 1) during direct shift mode (bit 32 = 0), the modulo value of the n-divider will be ignored (the new n-divider is then 2278 instead of 2278.25). this means that the pll locks on the next lower multiple frequency of 4 f pdf (in our case f pdf = 12.5 khz). the new vco frequency (f vco ) is then 113.9 mhz (instead of 113.9125 mhz in fractional mode). also the pll has additionally a special fractional logic which allows a good spurious suppression in the fractional and direct shift mode. activating the wire switch (bit 60 = 1) and the correction charge pump (bit 60 = 1) the spurious suppression is active. charge pump current settings bit 62 (0 = 1 ma; 1 = 2 ma) allows to adjust the high current, which is active during a fre- quency change (if the delay time of the active hcdel register is not switched off). a high charge pump current allows faster frequeny changes. after a frequency change, the current reduction is reduced (in locked mode) to the low current which is set by bit 63 (0 = 50 a; 1 = 100 a). a lower charge pump current guarantees a higher s/n ratio. the high current charge pump can be switched off by the active hcdel register bits. in this case, when hcdel 1 is active and the bits 20 and 21 are 0 (hcdel 1 delay time = off) or hcdel 2 is active and the bits 22 and 23 are 0 (hcdel 2 delay time = off), only the low current charge pump (current) is active in locked and in the frequency change mode.
23 t4260 4528b ? audr ? 04/02 am prescaler (divider) settings the am mixer is used for up-conversion of the am reception frequency to the if fre- quency. therefore, an am prescaler is implemented to generate the necessary lo from the vco frequency. for the reception of the am band, different prescaler (divider) set- tings are possible. the table 28 lists the am prescaler (divider) settings and the reception frequencies. f vco = 98.2 mhz to 124 mhz f if = 10.7 mhz f rec = f vco - f if table 28. am prescaler (divider) settings and the reception frequencies external voltage at amlf (pin 17) by using two ics, for example, it is possible to operate the amlf (pin 17) of the second ic either with the tuning voltage (vtune [pin 18]), the dac 1 voltage [pin 1] or the dac 2 voltage [pin 2] from the first t4260. for voltage reduction at the amlf [pin 17], a volt- age factor ratio of 100/16 (r1/r2) is required. this means that an applied voltage from 0.5 v at pin 17 (amlf) corresponds to a tuning voltage of 3.625 v. it is recommended to use r1 with 100 k ? and r2 with 16 k ? . the allowed range of r1 is 10 k ? to 1 m ? and 1.6 k ? to 160 k ? for r2. figure 11. external voltage at amlf (pin 17) divider (am prescaler) minimum reception frequency [mhz] maximum reception frequency [mhz] no divider 87.5 113.3 divide by 2 38.4 51.3 divide by 3 22.033 30.633 divide by 4 13.85 20.3 divide by 5 8.94 14.1 divide by 6 5.667 9.967 divide by 7 3.329 7.014 divide by 8 1.575 4.8 divide by 9 0.211 3.078 divide by 10 0 1.7 r1 gain vtune or dac r2 t4260 amlf t4260
24 t4260 4528b ? audr ? 04/02 figure 12. test circuit 10n 1 2 3 4 6 5 7 8 9 10 11 12 13 17 15 16 14 19 33 22 21 20 18 rfagca 2 rfagcfm sw2/agc ifagca2 amagco mxamia mxamib gndrf mxfmib mxfmia fmagco dac2 dac1 sw1 vrvco vspll fmlf amlf vtune oscgnd osce oscb oscbuf 34 35 36 37 32 38 39 40 41 42 43 44 31 30 29 28 27 26 23 24 25 ifref ifouta ifoutb gndpll ifagcfm mxamob gndt vrt ifagca1 ifinam ifinfm en clk data vrpll reffreq mxamoa mxfmob mxfmoa rfagca1 vst 10n test point 5k1 1n 100n 10k 1n vspll 47p 5k6 3k 330 100 100k 100n 2k4 330 vst bus 10n 10n 100n 10n 22p 15p 10n 10n 100k 100n 100n 10n
25 t4260 4528b ? audr ? 04/02 figure 13. application circuit 12 13 14 15 16 17 18 19 20 21 22 33 32 31 30 29 28 27 26 25 24 23 44 43 42 41 40 39 38 37 36 35 34 1 2 3 4 5 6 7 8 9 10 11 rfagca2 rfagcfm sw2/agc ifagca2 mxamia amagco mxamib gndrf mxfmib mxfmia fmagco dac2 dac1 sw1 vrvco vspll fmlf amlf vtune oscgnd osce oscb oscbuf ifagca1 ifref ifinam ifinfm vrt gndt mxamob mxamoa vst rfagca1 mxfmoa mxfmob ifagcfm ifouta ifoutb gndpll reffreq vrpll data clk en 18p f3 c24 c23 r14 68k c25 4n7 r11 68k r12 68k c20 10p c21 10n r10 47k l1 r9 470 c18 c22 2u2 c19 27p f4 bb804 cd2 c26 c27 10n c33 100n r13 1k 3p9 d1 s391d 10n l4 4u7 r17 47 c34 220n c36 10n t1 bfr93a s391d d2 s391d cd1 bb804 1n 6p8 c16 10n c17 10n c29 100n f5 c49 6p8 47p 22p r27 5k6 r16 2k7 r15 1k l3 2m2 l2 100uh c30 100n c31 12p c32 6p8 c38 100n r19 470k bc 848 t3 t4 c39 100n c40 15n c41 100n c42 1n c43 2n2 r24 6k2 r25 5k1 r26 100 c46 1n c5 220n c8 100n c10 100n c11 220n c12 100n kf1 kf2 clk p5 en p6 data p4 c14 100n c13 10uf r8 2k2 r6 300 r2 180 r3 300 f1 f2 r22 470k t2 bc848b c4 1u c7 100n r5 5r6 c2 100n c1 10u r1 5r6 vst p1 d3 c35 10p cd3 bb804 c47 c48 c9 100n r23 5r6 vspll p10 c44 100n c45 10u r18 470k dac1 p7 dac2 p8 amprein p14 p2 gndt p3 gndpll oscbuf bu5 reffreq bu4 ifouta bu2 ifoutb bu3 p15 sw1 c28 4u7 c37 2u2 p16 bu1 ant c15 100n oscb bu4 p11 fm p12 am p13 vt 1n c50 c6 c3 47p 100p j109 p9 amagco r28 3k9
26 t4260 4528b ? audr ? 04/02 package information ordering information extended type number package remarks t4260-il sso44 tube T4260-ILQ sso44 taped and reeled technical drawings according to din specifications package sso44 dimensions in mm 0.25 0.10 0.3 0.8 18.05 17.80 16.8 2.35 9.15 8.65 7.50 7.30 10.50 10.20 0.25 44 23 1 22
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